The present invention relates to a microcomputer configured in a single chip, which is provided with a plurality of modules activated by causing power to be supplied from an independent power source, and particularly relates to the control over its memories.
As the integration of an LSI device progresses, a chip configuring a system on silicon that is, a LSI called a System on Chip (SoC) has been realized.
The SoC often includes a memory inside the chip. With increasing storage capacity of the SoC memory, redundancy schemes implemented in the memory are instrumental in improving chip manufacturing yields (for example, refer to Japanese Patent Application Laid-open No. Hei 7-320495 and incorporated herein by reference). Accordingly, when a failure is found in an installed memory element during manufacturing test of the SoC, the defective memory elements are replaced with redundant memory elements (redundant bits). The replacement of memory elements is achieved by programming a fuse buried in the chip by a laser or by applying a programming current in the case of an eFuse.
Unlike a general-purpose memory, the SoC generally incorporates a variety of memory types. Therefore, when employing a configuration of one fuse for one memory element, the number of fuses increases dramatically and commensurately with the total chip area dedicated to redundancy fusing. Hence, employed is conventionally a configuration to realize a configuration (a control over replacement with redundancy memory elements) of a memory, where information for the redundancy of all memories inside a chip (configuration information) is stored in one fuse cell, and where the configuration information is propagated to each memory. Furthermore, as a data amount increases, the compression efficiency of data generally becomes more robust.
Accordingly, integrating fuse data (configuration information) in one cell can increase the efficiency of the data compression more than storing the fuse data in separate fuses.
FIG. 8 shows a schematic view of a configuration of a conventional SoC.
In an example shown in FIG. 8, all memories in a chip (data cache 812 and program cache 813 of module 810 and data cache 822 and program cache 823 of module 820) can switch a memory element to a redundancy memory element by the control of single fuse cell 801. In FIG. 8, configuration data stored in fuse cell 801 is compressed to reduce the total volume of configuration data. When turning on SoC 800, the compressed data is output from fuse cell 801 by Power on Reset, thus being decompressed by decompression 802.
Conversely, in the SoC of FIG. 8, each memory including a dynamic random access memory (DRAM) 803 is provided with shift registers (flip-flop circuits) depicted in FIG. 9. Further, the shift registers of the respective memories are connected together forming a scan chain. Moreover, the decompressed configuration data is propagated to DRAM 803 and each memory of the modules 810 and 820 by the scan chain.
Incidentally, an application specific integrated circuit (ASIC) designed and manufactured for a specific purpose, which is realized as a SoC, may have a power-saving design called a voltage island to reduce the power consumption as disclosed, for example, in “Design System Voltage Island”, IBM Japan, available at http:www-6.ibm.com/jp/chips/products/asics/products/v_island.html and incorporated herein by reference. In a voltage island based SoC architecture, a circuit in an ASIC is divided into a plurality of modules, thus making it possible to independently switch on and off the respective modules for which a power source is required. Then, by turning off a module which is not being used, the leakage current of the module can be eliminated. A cell phone operated in a standby mode, for example, may supply power only to those modules necessary for maintaining standby mode operation and turn off the power of a large unneeded part of a circuit with this technique. In this regard, it is possible to dramatically improving battery life of mobile devices by suppressing leakage current of an ASIC as much as possible.
In the SoC shown in FIG. 8, modules 810 and 820 represent discrete areas of the SoC with different voltage domains or voltage islands, respectively. Power is independently supplied from power source VDD1 to module 810, and from power source VDD2 to module 820 (in practice, the independent power sources VDD1 and VDD2 are realized by supplying power to the respective modules 810 and 820 from a power source VDD common to the whole SoC through independent switches). Hence, it is possible to turn off one of the modules 810 and 820 and activate the other independently, by turning off one of the power sources VDD1 and VDD2.
As described above, a voltage island with memory array redundancy and a power-saving design is realized in a SoC. However, when memory array redundancy is implemented on a SoC with different voltage islands, the following problems arise.
First, when turning on the whole SoC, all memories do not have information on a redundant circuit in an initial state. Therefore, a fuse/decompression module (i.e. fuse cell 801 and decompression 802 of FIG. 8) is initialized by Power on Reset.
Consequently, the data stored in fuse cell 801 is decompressed by the decompression 802, thus propagating the data to each memory by the scan chain. When finishing the transfer, the configuration of a memory is completed as shown in FIG. 10, thus reaching a state where a central processing unit (CPU) can access a memory.
If the function of module 820 becomes unnecessary shortly after turning on the power supplying the SoC, the power source VDD2 of module 820 is turned off to reduce power consumption. At this point, since the power supply is cut in module 820, the memory configuration information (the data cache 822 and the program cache 823) included in the module 820 is lost.
When an application using module 820 is thereafter executed, the power source VDD2 of module 820 is turned on again. However, since the configuration information on the memories residing in module 820 is lost, a fuse/decompression module must be initialized again to use the memories. Thus, the configuration information saved in the memories of module 820 must be propagated by the scan chain.
However, if the configuration information is propagated by this scan chain, the configuration information on the memories (the data cache 812 and the program cache 813) of module 810 is simultaneously rewritten. Hence, it temporarily becomes impossible to access the memories (including the DRAM 803) by a CPU 811 also in the module 810 until the configuration information is transferred by the scan chain.
A method implementing a fuse/decompression module for each domain can be considered. If there is a fuse/decompression module for each domain (module), the influence of the propagation of the configuration information does not affect any modules except for those that are currently being supplied power. Therefore, when module 820 is turned on as described above, the operations of module 810 are not disabled. However, such a configuration leads to an increase in the total area of a chip since a plurality of fuse/decompression modules which occupy an extremely large area on the chip are provided, and also since the effect of compressing data retained by fuse cells weakens due to the scattering of the fuse cells.